Publication

Fixed latency on-chip interconnect for hardware spiking neural network architectures

Pande, Sandeep
; 
Morgan, Fearghal
; 
Smit, Gerard
; 
Bruintjes, Tom
; 
Rutgers, Jochem
; 
McGinley, Brian
; 
Cawley, Seamus
; 
Harkin, Jim
; 
McDaid, Liam
Identifiers
http://hdl.handle.net/10379/13396
 https://doi.org/10.13025/25741
Publication Date
2013-09-01
Keywords
network on chip (noc), spiking neural networks (snn), synaptic connectivity, latency jitter, neurons, implementations, platform, design
Type
Article
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Citation
Pande, Sandeep; Morgan, Fearghal; Smit, Gerard; Bruintjes, Tom; Rutgers, Jochem; McGinley, Brian; Cawley, Seamus; Harkin, Jim; McDaid, Liam (2013). Fixed latency on-chip interconnect for hardware spiking neural network architectures. Parallel Computing 39 (9), 357-371
Abstract
Funder
Publisher
Elsevier BV
Publisher DOI
Rights
Attribution-NonCommercial-NoDerivs 3.0 Ireland
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Externally hosted open access publications with University of Galway authors (2)